View CYUSB3014_2033054.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary CYUSB3014 ez-usb ? fx3 superspeed usb controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number 001-52136 rev. *h revised may 17, 2011 features universal serial bus (usb) integration ? usb 3.0 and usb 2.0 peripheral compliant with usb3.0 specification 1.0 ? 5-gbps usb3.0 phy co mpliant with pipe 3.0 ? high-speed on-the-go (hs-otg) host and peripheral compliant with on-the-go supplement version 2.0 ? thirty-two physical endpoints ? support for battery charging spec 1.1 and accessory charger adaptor (aca) detection general programmable interface (gpif? ii) ? programmable 100-mhz gpif ii interface enables connectivity to wide range of external devices ? 8-/16-/32-bit data bus ? up to 16 configurable control signals fully accessible 32-bit cpu ? arm926ej core with 200mhz operation ? 512 kb embedded sram additional connectivity to following peripherals ? i 2 c master controller at 1 mhz ? i 2 s master (transmitter only) at sampling frequencies 32 khz, 44.1 khz, 48 khz ? uart support up to 4 mbps ? spi master at 33 mhz selectable clock input frequencies ? 19.2, 26, 38.4, and 52 mhz ? 19.2 mhz crystal input support ultra low-power in core power-down mode ? less than 60 a with vbatt on and 20 a with vbatt off independent power domains for core and i/o ? core operation at 1.2 v ? i 2 s, uart and spi operation at 1.8 to 3.3v ? i 2 c operation at 1.2 v 10 10 mm, 0.8 mm pitch pb-fr ee ball grid array (bga) package ez usb ? software and dvk for easy code development applications digital video camcorders digital still cameras printers scanners video capture cards test and measurement equipment surveillance cameras personal navigation devices medical imag ing devices video ip phones portable media players industrial cameras 32 eps gpif? ii hs/fs per ipheral ss per ipheral hs/fs/ls otg host arm 926 ej -s jtag uart spi i2s embedded sram (512kb) us b i nte rfa ce ez-dtect? ctl[12 :0 ] int# reset # tdi tdo trst# tms tck data[31:0 ] pmode[2:0 ] otg_ id ssrx - ssrx + sstx - sstx + d+ d- fslc[0] fslc[1] fslc[2] clkin clkin_32 xtalin xtalout i2c_s cl i2c_sda tx rx cts rts i2s _clk i2 s_s d i2s_ws i2 s_ ms cl k ss n sck miso mosi i2c logic block diagram [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 2 of 38 contents functional overview .......................................................... 3 application examples .................................................... 3 usb interface ...................................................................... 4 otg............................................................................... 4 renumeration ............................................................... 5 ez-dtect ........................................................................ 5 vbus overvoltage protection .... .............. .............. ....... 5 carkit uart mode ........................................................ 5 gpif ii .................................................................................. 6 cpu ...................................................................................... 6 jtag interface .................................................................... 7 other interfaces .................................................................. 7 uart interface.............................................................. 7 i2c interface.................................................................. 7 i2s interface .................................................................. 7 spi interface.................................................................. 7 boot options....................................................................... 7 reset.................................................................................... 8 hard reset .................................................................... 8 soft reset...................................................................... 8 clocking .............................................................................. 8 32-khz watchdog timer clock i nput................ ............. 8 power................................................................................... 9 power modes ................................................................ 9 configuration options ..................................................... 13 digital i/os......................................................................... 13 gpios................................................................................. 13 system level esd ............................................................ 13 absolute maximum ratings ............................................ 14 operating conditions....................................................... 14 ac timing parameters ............. ........................................ 16 gpif ii timing ............................................................. 16 slave fifo interface ................................................... 19 serial peripherals timing ....... ..................................... 26 reset sequence.......... .............. ........... ........... ............ ...... 30 pin description ................................................................. 32 package diagram.............................................................. 35 ordering information ....................................................... 35 ordering code definition........ ..................................... 35 acronyms .......................................................................... 36 document conventions ................................................... 36 units of measure ......................................................... 36 document history page ................................................... 37 sales, solutions, and legal information ........................ 38 worldwide sales and design supp ort............. ............ 38 products ...................................................................... 38 psoc solutions ........................................................... 38 [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 3 of 38 functional overview cypress ez-usb fx3 is the next generation usb3.0 peripheral controller providing highly integrated and flexible features that enable developers to add usb3.0 functionality to any system. ez-usb fx3 has a fully configurable, parallel, general programmable interface called gpif ii, which can connect to any processor, asic, or fp ga. the general programmable interface gpif ii is an enhanc ed version of the gpif in fx2lp, cypress?s flagship usb2.0 product. it provides easy and glueless connectivity to popular interfaces such as asynchronous sram, asynchronous and synchronous address data multiplexed interface, parallel ata, and so on. ez-usb fx3 has integrated usb3.0 and usb2.0 physical layer (phys) along with a 32-bit arm926ej-s microprocessor for powerful data processing and for building custom applications. it implements an ingenious architecture which enables data transfers of 320 mbps [1] from gpif ii to usb interface. an integrated usb2.0 otg controller enables applications that need dual role usage scenarios, for example ez-usb fx3 may function as otg host to msc and hid class devices. ez-usb fx3 contains 512 kb of on-chip sram for code and data. ez-usb fx3 also provides interfaces to connect to serial peripherals such as uart, spi, i 2 c, and i 2 s. ez-usb fx3 comes with the easy to use ez-usb tools providing a complete solution for fast application development. the software development kit comes with application examples for accelerating time to market. ez-usb fx3 is fully compliant to usb3.0 v1.0 specification and is also backward compatible with usb2.0. it is also complaint with the battery charging specification v1.1 and usb2.0 otg specification v2.0. application examples figure 1 and figure 2 show typical application diagrams for ez-usb fx3. figure 1 shows a typical application diagram in which ez-usb fx3 functions as a co-processor and connects to an external processor responsible for various system level functions. figure 2 shows a typical application diagram when ez-usb fx3 functions as the ma in processor in the system. figure 1. ez-usb fx3 as a co-processor note 1. assuming that gpif ii is configured for 32 bit data bus synchr onous interface operating at 100 mhz. this number also includes protocol overheads. ez-usb fx3 (arm9 core) external serial peripheral (example: eeprom) crystal* power subsystem xtalin xtalout gpif ii text external processor (example: mcu/cpu/asic/ fpga) serial interfaces (example: i2c) usb port usb host * a clock input may be provided on the clkin pin instead of a crystal input [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 4 of 38 figure 2. ez-usb fx 3 as main processor usb interface ez-usb fx3 supports usb peripheral functionality compliant with usb 3.0 specification revi sion 1.0 and is also backward compatible with the usb 2.0 specification. ez-usb fx3 is compliant with on-the-go supplement revision 2.0. it supports hi-speed, full-speed, and low speed otg dual role device capability. it is superspeed, high-speed, and full-speed capable as a peripheral and high-speed, full-speed, and low-speed capable as a host. ez-usb fx3 supports carkit pass-through uart functionality on usb d+/d- lines based on the cea-936a specification. ez-usb fx3 supports up to 16 in and 16 out endpoints. ez-usb fx3 fully supports the usb3.0 streams feature. it also supports usb attached scsi (u as) device class to optimize mass storage access performance. as a usb peripheral, ez-usb fx3 supports uas, usb video class (uvc), mass storage class (msc), and media transfer protocol (mtp) usb peripheral classes. as a usb peripheral, all other device classes are supported only in pass through mode when handled entirely by a host processor external to the device. as an otg host, ez-usb fx3 supports msc and hid device classes. when the usb port is not in use, the phy and transceiver may be disabled for power savings. figure 3. usb interface signals otg ez-usb fx3 is compliant with the on-the-go (otg) specifi- cation revision 2.0 . in otg mode, ez-usb fx3 supports both a and b device mode and supports control, interrupt, bulk, and isochronous data transfers. ez-usb fx3 requires an external charge pump (either stand alone or integrated into a pmic) to power vbus in otg a-device mode. the target peripheral list for otg host implementation consists of msc and hid class devices. attach detection protocol (adp) is not supported by ez-usb fx3. external slave device (eg: image sensor) ez-usb fx3 (arm9 core) gpif ii i2c usb port crystal* xtalin xtalout usb host eeprom * a clock input may be provided on the clkin pin instead of a crystal input ez-usb fx3 vbatt vbus usb interface ssrx- ssrx+ sstx- sstx+ d- d+ otg_id [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 5 of 38 otg connectivity in otg mode, ez-usb fx3 can be configured to be a, b, or dual role device. it is able to connect to: aca device targeted usb peripheral srp capable usb peripheral hnp capable usb peripheral otg host hnp capable host otg device renumeration because ez-usb fx3's configuration is soft, one chip can take on the identities of multip le distinct usb devices. when first plugged into usb, ez-usb fx3 enumerates automatically with the cypress vendor id (0x04b4) and downloads firmware and usb descriptors over the usb interface. the downloaded firmware executes a electrical disconnect and connect. ez-usb fx3 enumerates again, this time as a device defined by the downloaded information. this patented two step process called renumeration happens instantly when the device is plugged in. ez-dtect ez-usb fx3 supports usb charger and accessory detection (ez-dtect). the charger detection mechanism is in compliance with the battery charging specif ication revision 1.1. in addition to supporting this version of the specification ez-usb fx3 also provides hardware support to detect the resistance values on the id pin. the following are the resistance ranges that ez-usb fx3 can detect: less than 10 less than 1 k 65 k to 72 k 35 k to 39 k 99.96 k to 104.4 k (102 k 2%) 119 k to 132 k higher than 220 k 431.2 k to 448.8 k (440 k 2%) ez-usb fx3's charger detection feature detects a dedicated wall charger, host/hub charger, and host/hub. vbus overvoltage protection the maximum input voltage on ez-usb fx3's vbus pin is 6v. a charger can supply up to 9v on vbus, in this case, it is necessary to have an external over voltage protection (ovp) device to protect ez-usb fx3 from damage on vbus. figure 4 shows the system application diagram with an ovp device connected on vbus. please refer to ta b l e 7 dc specifications for the operating range of vbus and vbatt. figure 4. system diagram with ovp device for vbus carkit uart mode the usb interface supports carkit uart mode (uart over d+/d-) for non-usb serial data transfer. this is based on the cea-936a specification. in carkit uart mode, the output signaling voltage is 3.3v. when configured for carkit uart mode, txd of uart (output) is mapped to d- line, and rxd of uart (input) is mapped to d+ line. in carkit mode, ez-usb fx3 disables the usb transceiver and d+ and d- pins serve as pass through pins to connect to the uart of the host processor. the carkit uart signals may be routed to the gpif ii interface or to gpio[48] and gpio[49] as shown in figure 5 on page 6. a rate of up to 9600 bps is supported by ez-usb fx3 in this mode. power subsystem usb connector ez-usb fx3 usb-port 1 8 2 3 4 5 6 7 9 vbus gnd ssrx- ssrx+ sstx- sstx+ d- d+ otg_id vdd vio1 cvddq vio2 vio3 avdd vio5 ovp device vio4 u3txvddq u3rxvddq [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 6 of 38 figure 5. carkit uart pass through block diagram gpif ii ez-usb fx3 offers a high performance general programmable interface, gpif ii. this interfac e enables functionality similar to but more advanced than fx2lp's gpif and slave fifo interfaces. the gpif ii is a programmable state machine that enables a flexible interface that may functi on either as a master or slave in industry standard or proprietary interfaces. both parallel and serial interfaces may be implemented with gpif ii. the features of the gpif ii are summarized as follows: functions as master or slave provides 256 firmware programmable states supports 8 bit, 16 bit and 32 bit parallel data bus enables interface frequencies up to 100 mhz. supports 14 configurable control pins when 32 bit data bus is used. all control pins can be either input/output or bidirectional. supports 16 configurable control pins when 16/8 data bus is used. all control pins can be eith er input/output or bidirectional. gpifii state transitions occur bas ed on control input signals. the control output signals are driven as a result of gpifii state transi- tions. the behavior of the gpifii state machine is defined by a gpifii descriptor. the gpifii descriptor is designed such that the required interface specificat ions are met. 8kb of memory (separate from the 512kb of embedded sram) is dedicated as gpif ii waveform memory where t he gpif ii descriptor is stored in a specific format. cypress? gpifii designer tool enables fast development of gpifii descriptors and includes examples for common inter- faces. example implementations of gpif ii are the asynchronous slave fifo and synchronous slave fifo interfaces. slave fifo interface the slave fifo interface signals are shown in figure 6 . this interface allows an external processor to directly access upto 4 buffers internal to ez-usb fx3. further details of the slave fifo interface are described on page 19 note: access to all 32 buffer is also supported over slave fifo interface. for details, please contact cypress applications support. figure 6. slave fifo interface cpu ez-usb fx3 has an on chip 32-bit, 200 mhz arm926ej-s core cpu. the core has dire ct access to 16kb of instruction tightly coupled memory (tcm) and 8kb of data tcm. the arm926ej-s core provides a jtag interface for firmware debugging. ez-usb fx3 also integrates 512 kb of embedded sram for code and data, and 8kb of instruction cache and data cache. ez-usb fx3 implements highly efficient and flexible dma connectivity between the various pe ripherals (i.e. usb, gpif ii, i 2 s, spi,uart), requiring firmware to only configure data accesses between peripherals which are then managed by the dma fabric. ez-usb fx3 allows for easy application development on industry standard development tools for arm926ej-s. examples of ez-usb fx3 firmware are available with the cypress ez-usb fx3 development kit. software apis that can be ported to an external processor are available with the cypress ez-usb fx3 software development kit. carkit uart pass through carkit uart pass through interface on gpif (tm) ii interface. rxd (dp) txd (dm) usb phy dp dm txd rxd usb-port mux uart_txd uart_rxd gpio[48] (uart_tx) gpio[49] (uart_rx) carkit uart pass through interface on gpios ctrl external processor ez-usb fx3 slcs# a[1:0] d[31:0] slrd# sloe# slwr# pktend flaga flagb note: multiple flags may be configured. [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 7 of 38 jtag interface ez-usb fx3?s jtag interface provides a standard five-pin interface for connecting to a jtag debugger to debug firmware through the cpu-core's on-chip-debug circuitry. industry standard debugging tools for the arm926ej-s core can be used for ez-usb fx3 application development. other interfaces ez-usb fx3 supports the following serial peripherals: uart i 2 c i 2 s spi the spi, uart and i 2 s interfaces are multiplexed on the serial peripheral port. the pin list on page 32 shows details of how these interfaces are multiplexed. uart interface the uart interface of ez-usb fx3 supports full duplex communication. it includes the signals noted in ta b l e 1 . the uart is capable of generating a range of baud rates from 300 bps to 4608 kbps selectable by the firmware. i 2 c interface ez-usb fx3 has an i 2 c interface compatible with the i 2 c bus specification revision 3. ez-usb fx3?s i 2 c interface is capable of operating as i 2 c master only, hence may be used to communicate with other i 2 c slave devices. for example, ez-usb fx3 may boot from an eeprom connected to the i 2 c interface, as a selectable boot option. ez-usb fx3?s i 2 c master controller also supports multi-master mode functionality. the power supply for the i 2 c interface is vio5, which is a separate power domain from the other serial peripherals. this is to allow the i 2 c interface the flexibility to operate at a different voltage than the other serial interfaces. the bus frequencies supported by the i 2 c controller are 100 khz, 400 khz, and 1 mhz. when vio5 is 1.2v, the maximum operating frequency supported is 100 khz. when vio5 is 1.8 v, 2.5 v or 3.3 v, the operating fr equencies supported are 400 khz and 1 mhz. both scl and sda signals of the i 2 c interface require external pull-up resistors. the pull-up resistors must be connected to vio5. i 2 s interface ez-usb fx3 has an i 2 s port to support external audio codec devices. ez-usb fx3 functions as i 2 s master as transmitter only. the i 2 s interface consists of four signals: clock line (i2s_clk), serial data line (i2s _sd), word select line (i2s_ws), and master system clock (i 2s_mclk). ez-usb fx3 can generate the system clock as an output on i2s_mclk or accept an external system clock input on i2s_mclk. the sampling frequencies supported by the i 2 s interface are 32 khz, 44.1 khz, and 48 khz. spi interface ez-usb fx3 supports an spi master interface on the serial peripherals port.the maximum frequency of operation is 33 mhz. the spi controller supports four modes of spi communication with start-stop clock. the spi controller is a single master controller with a single automat ed ssn control. it supports transaction sizes from 4-bit to 32 bits long. boot options ez-usb fx3 can load boot images from various sources, selected by the configuration of the pmode pins. the boot options for ez-usb fx3 are listed as follows: boot from usb boot from i 2 c boot from spi (spi devices supported are m25p16 (16 mbit), m25p80 (8 mbit), and m25p40 (4 mbit)) or their equivalents boot from gpif ii async admux mode boot from gpif ii sync admux mode boot from gpif ii async sram mode table 1. uart interface signals signal description tx output signal rx input signal cts flow control rts flow control table 2. booting options for ez-usb fx3 pmode[2:0] [2] boot from f00 sync admux (16-bit) f01 async admux (16-bit) f11 usb boot f0f async sram (16-bit) f1f i 2 c, on failure, usb boot is enabled 1ff i 2 c only 0f1 spi, on failure, usb boot is enabled note 2. f indicates floating. [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 8 of 38 reset hard reset a hard reset is initiated by asserting the reset# pin on ez-usb fx3. the specific reset sequence and timing requirements are detailed in figure 17 and ta b l e 1 5 . soft reset soft reset involves the processor setting the appropriate bits in the pp_init control register. ther e are two types of soft reset: cpu reset - the cpu program c ounter is reset. firmware does not need to be reloaded following a cpu reset. whole device reset - this reset is identical to hard reset. the firmware must be reloaded following a whole device reset. clocking ez-usb fx3 allows either a crystal to be connected between the xtalin and xtalout pins or an external clock to be connected at the clkin pin. crystal frequency supported is 19.2 mhz, while the external clock frequencies supported ar e 19.2, 26, 38.4, and 52 mhz. ez-usb fx3 has an on-chip oscillator circuit that uses an external 19.2 mhz (100 ppm) crystal (when the crystal option is used). the fslc[2:0] pins must be configured appropriately to select the crystal option/clo ck frequency option. the configu- ration options are shown in ta b l e 3 . clock inputs to ez-usb fx3 must meet the phase noise and jitter requirements specified in table 4 . the input clock frequency is independent of the clock/data rate of ez-usb fx3 core or any of the device interfaces (including p-port and s-port). the internal pll applies the appropriate clock multiply option depending on the input frequency. 32-khz watchdog timer clock input ez-usb fx3 includes a watchdog timer. the watchdog timer can be used to interrupt the arm926ej-s core, auto wakeup ez-usb fx3 in standby mode and reset the arm926ej-s core. the watch dog timer runs off a 32 khz clock. this 32 khz clock may optionally be supplied from an external source on a dedicated pin of ez-usb fx3. the watchdog timer can be disabled by firmware. requirements for the optional 32 khz clock input are listed in ta b l e 5 . table 3. crystal/clock frequency selection fslc[2] fslc[1] fslc[0] crystal/ clock frequency 0 0 0 19.2 mhz crystal 1 0 0 19.2 mhz input clk 1 0 1 26 mhz input clk 1 1 0 38.4 mhz input clk 1 1 1 52 mhz input clk table 4. input clock specifications for ez-usb fx3 parameter description specification units min max phase noise 100 hz offset ? ?75 db 1 khz offset ? ?104 db 10 khz offset ? ?120 db 100 khz offset ? ?128 db 1 mhz offset ? ?130 db maximum frequency deviation ? 150 ppm duty cycle 30 70 % overshoot ? 3 % undershoot ? ?3 % rise time/fall time ? 3 ns table 5. 32 khz clock input requirements parameter min max units duty cycle 40 60 % frequency deviation ? 200 ppm rise time/fall time ? 3 ns [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 9 of 38 power ez-usb fx3 has the following power supply domains. io_vddq : this refers to a group of independent supply domains for digital i/os. the voltage level on these supplies is 1.8v to 3.3v. ez-usb fx3 provides six independent supply domains for digital i/os listed as follows. refer to ta b l e 1 6 for details on the signals assigned to each power domain. vio1 - gpif ii i/o power supply domain vio2 - io2 power supply domain vio3 - io3 power supply domain vio4 - uart/spi/i 2 s power supply domain vio5 - i 2 c and jtag power supply domain (1.2v to 3.3v is supported) cvddq - clock power supply domain v dd : this is the supply voltage for the logic core. the nominal supply voltage level is 1.2 v. this supplies the core logic circuits. the same supply must also be used for the following: ? avdd : this is the 1.2 v supply for the pll, crystal oscillator and other core analog circuits ? u3txvddq/u3rxvddq : these are the 1.2 v supply volt- ages for the usb 3.0 interface. vbatt/vbus : this is the 3.2v to 6v battery power supply for the usb i/o, and analog circuits. this supply powers the usb transceiver through ez-usb fx3's internal voltage regulator. vbatt is internally regulated to 3.3v. power modes ez-usb fx3 supports different power modes as follows: normal mode: this is the full func tional operating mode. in this mode the internal cpu clock and the internal plls are enabled. normal operating power consumption does not exceed the sum of icc_core max and icc_usb max (please refer to table 7 for current consumpt ion specifications). the i/o power supplies (vio1,v io2,vio3,vio4, vio5) may be turned off when the corresponding interface is not in use. ez-usb fx3 supports four low power modes: suspend mode with usb 3.0 phy enabled (l1) suspend mode with usb 3.0 phy disabled (l2) standby mode (l3) core power down mode (l4) [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 10 of 38 the different low power modes are described in ta b l e 6 .. table 6. entry and exit methods for low power modes low power mode characteristics methods of entry methods of exit suspend mode with usb 3.0 phy enabled (l1) the power consumption in this mode does not exceed isb 1 usb 3.0 phy is enabled and is in u3 mode (one of the suspend modes defined by the usb3.0 specification). this one block alone is opera- tional with its internal clock while all other clocks are shut down all i/os maintain their previous state power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually the states of the configuration registers, buffer memory and all internal ram are maintained all transactions must be completed before ez-usb fx3 enters suspend mode (state of outstanding transac- tions are not preserved) the firmware resumes operation from where it was suspended (except when woken up by reset# assertion) because the program counter does not reset firmware executing on arm926ej-s core can put ez-usb fx3 into suspend mode. for example, on usb suspend condition, firmwar e may decide to put ez-usb fx3 into suspend mode external processor, through the use of mailbox registers can put ez-usb fx3 into suspend mode d+ transitioning to low or high d- transitioning to low or high impedance change on otg_id pin resume condition on ssrx +/- detection of vbus level detect on uart_cts (programmable polarity) gpif ii interface assertion of ctl[0] assertion of reset# [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 11 of 38 suspend mode with usb 3.0 phy disabled (l2) the power consumption in this mode does not exceed isb 2 usb 3.0 phy is disabled and the usb interface is in suspend mode the clocks are shut off. the plls are disabled all i/os maintain their previous state usb interface maintains the previous state power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually the states of the configuration registers, buffer memory and all internal ram are maintained all transactions must be completed before ez-usb fx3 enters suspend mode (state of outstanding transac- tions are not preserved) the firmware resumes operation from where it was suspended (except when woken up by reset# assertion) because the program counter does not reset firmware executing on arm926ej-s core can put ez-usb fx3 into suspend mode. for example, on usb suspend condition, firmwar e may decide to put ez-usb fx3 into suspend mode external processor, through the use of mailbox registers can put ez-usb fx3 into suspend mode d+ transitioning to low or high d- transitioning to low or high impedance change on otg_id pin resume condition on ssrx +/- detection of vbus level detect on uart_cts (programmable polarity) gpif ii interface assertion of ctl[0] assertion of reset# table 6. entry and exit methods for low power modes (continued) low power mode characteristics methods of entry methods of exit [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 12 of 38 standby mode (l3) the power consumption in this mode does not exceed isb3 all configuration register settings and program/data ram contents are preserved. however, data in the buffers or other parts of the data path, if any, is not guaranteed. therefore, the external processor should take care that needed data is read before putting ez-usb fx3 into this standby mode the program counter is reset on waking up from standby mode gpio pins maintain their configuration crystal oscillator is turned off internal pll is turned off usb transceiver is turned off arm926ej-s core is powered down. upon wakeup, the core re-starts and runs the program stored in the program/data ram power supply for the wakeup source and core power must be retained. all other power domains can be turned on/off individually firmware executing on arm926ej-s core or external processor configures the appro- priate register detection of vbus level detect on uart_cts (programmable polarity) gpif ii interface assertion of ctl[0] assertion of reset# core power down mode (l4) the power consumption in this mode does not exceed isb 4 core power is turned off all buffer memory, configu- ration registers and the program ram do not maintain state. it is necessary to reload the firmware on exiting from this mode in this mode, all other power domains can be turned on/off individually turn off v dd reapply vdd assertion of reset# table 6. entry and exit methods for low power modes (continued) low power mode characteristics methods of entry methods of exit [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 13 of 38 configuration options configuration options are availa ble for specific usage models. contact cypress applications/marketing for details. digital i/os ez-usb fx3 provides firmware controlled pull up or pull down resistors internally on all digital i/o pins. the pins can be pulled high through an internal 50 k resistor or can be pulled low through an internal 10 k resistor to prevent the pins from floating. the i/o pins may have the following states: tristated (high-z) weak pull up (via internal 50 k ) pull down (via internal 10 k ) hold (i/o hold its value) when in low power modes the jtag signals tdi, tmc, trst# signals have fixed 50 k internal pull-ups & the tck signal has a fixed 10 k pull down resistor. gpios ez-usb allows for a flexible pin configuration both on the gpif ii and the serial peripheral interfaces. any unused control pins on the gpif ii interface may be used as gpios. similarly, any unused pins on the serial peripheral interfaces may be configured as gpios. please refer to the pin list for pin config- uration options. all gpif ii and gpio pins support an external load of up to 16pf per pin. emi ez-usb fx3 meets emi requirements outlined by fcc 15b (usa) and en55022 (europe) for consumer electronics. ez-usb fx3 can tolerate reasonable emi conducted by aggressor outlined by these specifications and continue to function as expected. system level esd ez-usb fx3 has built-in esd protection on the d+, d-, gnd pins on the usb interface. the esd protection levels provided on these ports are: 2.2 kv human body model (hbm) based on jesd22-a114 specification 6 kv contact discharge and 8 kv air gap discharge based on iec61000-4-2 level 3a 8 kv contact discharge and 15 kv air gap discharge based on iec61000-4-2 level 4c. this protection ensures the device will continue to function after esd events up to the levels stated. the ssrx+, ssrx-, sstx+, sstx- pins only have up to +/- 2.2kv human body model (hbm) internal esd protection. [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 14 of 38 absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. storage temperature............................... ...... ?65 c to +150 c ambient temperature with power supplied (industrial)............. ....... ... ...... ?40 c to +85 c supply voltage to ground potential v dd , avddq ....................................................................... tbd vio1,vio2, vio3, vio4, vio5.......................................... ...tbd u3txvddq, u3rxvddq......................................... ..... .....tbd dc input voltage to any input pin. ............ ................ ........... .tbd dc voltage applied to outputs in high z state.................... ..................................... tbd static discharge voltage esd protection levels................ ............................................ 2.2 kv human body model (hbm) based on jesd22-a114 additional esd protection levels on d+, d-, gnd pins and serial peripheral s pins................. ........... 6 kv contact discharge, 8 kv air gap discharge based on iec61000-4-2 level 3a and 8 kv contact discharge, 15 kv air gap discharge based on iec61000-4-2 level 4c latch up current...........................................................> 200 ma maximum output short circuit current for all i/o configurations. (vout = 0v)[1].................... .. ?100 ma operating conditions t a (ambient temperature under bias) industrial....................................................... .. ?40 c to +85 c v dd , avddq, u3txvddq, u3rxvddq supply voltage................................................ ...1.15 v to 1.25 v vbatt supply voltage.......................... ....................3.2 v to 6 v vio1, vio2, vio3, vio4, cvddq supply voltage.................................................... ...1.7 v to 3.6 v vio5 supply voltage...................... .................... 1.15 v to 3.6 v table 7. dc specifications parameter description min max units notes v dd core voltage supply 1.15 1.25 v 1.2 v typical avdd analog voltage supply 1.15 1.25 v 1.2 v typical vio1 gpif ii i/o power supply domain 1.7 3.6 v 1.8, 2.5 and 3.3 v typical vio2 io2 power supply domain 1.7 3. 6 v 1.8, 2.5 and 3.3 v typical vio3 io3 power supply domain 1.7 3. 6 v 1.8, 2.5 and 3.3 v typical vio4 uart/spi/i2s power supply domai n 1.7 3.6 v 1.8, 2.5 and 3.3 v typical vbatt usb voltage supply 3.2 6 v 3.7 v typical vbus usb voltage supply 4.1 6 v 5 v typical u3txvddq usb3.0 1.2-v supply 1.15 1.25 v 1.2 v typical u3rxvddq usb3.0 1.2-v supply 1.15 1.25 v 1.2 v typical cvddq clock voltage supply 1.7 3.6 v 1.8,3.3 v typical vio5 i 2 c and jtag voltage supply 1.15 3.6 v 1.2,1.8, 2.5 and 3.3 v typical vih1 input high voltage 1 0.625 vcc vcc + 0.3 v for 2.0v vcc 3.6 v (except usb port) vih2 input high voltage 2 vcc ? 0.4 vcc + 0.3 v for 1.7 v vcc 2.0 v (except usb port) vil input low voltage ?0.3 0.25 vcc v voh output high voltage 0.9 vcc ? v ioh (max)= ?100 a vol output low voltage ? 0.1 vcc v iol(min) = +100 a iix input leakage current ?1 1 a al l i/o signals held at vddq (for i/os that have a pull-up/down resistor connected, the leakage current increases by vddq/r pu or vddq/r pd ioz output high-z leakage current ?1 1 a all i/o signals held at vddq [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 15 of 38 icc core core and analog voltage operating current ? 200 ma total current through avdd, vdd icc usb usb voltage supply operating current ? 60 ma isb1 total suspend current during suspend mode with usb 3.0 phy enabled (l1) ? ? ma core current: 1.5 ma io current: 20 ua usb current: 2 ma for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 c.) isb2 total suspend current during suspend mode with usb 3.0 phy disabled (l2) ? ? ma core current: 250 ua io current: 20 ua usb current: 1.2 ma for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 c.) isb3 total standby current during standby mode (l3) ? ? a core current: 60 ua io current: 20 ua usb current: 40 ua for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 c.) isb4 total standby current during core power-down mode (l4) ? ? a core current: 0 ua io current: 20 ua usb current: 40 ua for typical pvt (typical silicon, all power supplies at their respective nominal levels at 25 c.) v ramp voltage ramp rate on core and i/o supplies 0.2 50 v/ms voltage ramp must be monotonic v n noise level permitted on v dd and i/o supplies ? 100 mv max p-p noise level permitted on all supplies except avdd v n_avdd noise level permitted on avdd supply ? 20 mv max p-p noise level permitted on avdd table 7. dc specifications (continued) parameter description min max units notes [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 16 of 38 ac timing parameters gpif ii timing figure 7. gpif ii timing in synchronous mode - ctl (out) ctl(in) ts th tdh tds tclk clk tctlo tcoe data (in) data1 (out) thz tlz tdoh tcoh tclkh tclkl tlz data2 (out) tco tdoh dq[31:0] note 3. all parameters guaranteed by design and validated through characterization. table 8. gpif ii timing parameters in synchronous mode [3] parameter description min max unit frequency interface clock frequency ? 100 mhz tclk interface clock period 10 ? ns tclkh clock high time 4 ? ns tclkl clock low time 4 ? ns ts ctl input to clock setup time (sync speed =1) 2?ns th ctl input to clock hold time (sync speed =1) 0.5 ? ns tds data in to clock setup time (sync speed =1) 2?ns tdh data in to clock hold time (sync speed =1) 0.5 ? ns tco clock to data out propagation delay when dq bus is already in output direction(sync speed =1) ?8ns tcoe clock to data out propagation delay when dq lines change to output from tristate and valid data is available on the dq bus (sync speed =1) -9 tctlo clock to ctl out propagation delay (sync speed =1) ? 8 ns tdoh clock to data out hold 2 ? ns tcoh clock to ctl out hold 0 ? ns thz clock to high-z ? 8 ns tlz clock to low-z (sync speed =1) 0 ? ns ts_ss0 ctl input/data input to clock setup time (sync speed = 0) 5 ? ns th_ss0 ctl input/data input to clock hold time (sync speed = 0) 2.5 ? ns tco_ss0 clock to data out / ctl out propagation delay (sync speed = 0) ?15ns tlz_ss0 clock to low-z (sync speed = 0) 2 ? ns [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 17 of 38 figure 8. gpif ii timing in asynchronous mode figure 9. gpif ii timing in asynchronous ddr mode data/ addr ctl# (i/p , ale/ dle) tchz tctlalpha tctlbeta tdh/ tah tctldeassert_dqlatch tctldeassert data in tctlassert_dqlatch tchz/toehz tclz/ toelz tds/ tas data out data out ctl# (i/p, non ale/ dle alpha o/p beta o/p tctl# (o/p) tctlassert + n * tgranularity tctldeassert + n * tgranularity 11 1. n is an integer >= 0 taa/tdo tctlassert data/ addr ctl# i/p (non dle/ale) tdst tdht tctlassert_dqassert tctldeassert_dqassert data in ctl# (i/p) tds tctlassert_dqlatchddr tctldeassert_dqlatchddr tdh tds tdh [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 18 of 38 note 4. all parameters guaranteed by design and validated through characterization. table 9. gpif ii timing in asynchronous mode [4] note the following parameters assume one state transition parameter description min max units notes tds data in to dle setup time. valid in ddr async also. 2.3 ? ns tdh data in to dle hold ti me. valid in ddr async mode. 2?ns tas address in to ale setup time 2.3 ? ns tah address in to ale hold time 2 ? ns tctlassert ctl i/o asserted width for ctrl inputs without dq input association and for outputs. 7?ns tctldeassert ctl i/o deasserted width for ctrl inputs without dq input association and for outputs. 7?ns tctlassert_dqassert ctl asserted pulse width for ctl inputs that signify dq inputs valid at the asserting edge but do not employ in-built latches (ale/dle) for those dq inputs. 20 ? ns tctldeassert_dqassert ctl deasserted pulse width for ctl inputs that signify dq input valid at the asserting edge but do not employ in-built latches (ale/dle) for those dq inputs. 7?ns tctlassert_dqdeassert ctl asserted pulse width for ctl inputs that signify dq inputs valid at the de-asserting edge but do not employ in-built latches (ale/dle) for those dq inputs. 7?ns tctldeassert_dqdeassert ctl deasserted pulse width for ctl inputs that signify dq inputs valid at the deasserting edge but do not employ in-built latches (ale/dle) for those dq inputs. 20 ? ns tctlassert_dqlatch ctl asserted pulse width for ctl inputs that employ in-built latches (ale/dle) to latch the dq inputs. in this non_ddr case, in-built latches always close at the de-asserting edge. 7?ns tctldeassert_dqlatch ctl deasserted pulse width for ctl inputs that employ in-built latches (ale/dle) to latch the dq inputs. in this non-ddr case, in-built latches always close at the de-asserting edge. 10 ? ns tctlassert_dqlatchddr ctl asserted pulse width for ctl inputs that employ in-built latches (dle) to latch the dq inputs in ddr mode. 10 ? ns tctldeassert_dqlatchddr ctl deasserted pulse width for ctl inputs that employ in-built latches (dle) to latch the dq inputs in ddr mode. 10 ? ns tgranularity granularity of tc tlassert/tctldeassert for all outputs 5 ? ns at 200 mhz internal clock taa dq/ctl input to dq output time when dq change or ctl change needs to be detected and affects internal updates of input and output dq lines. ?30ns tdo ctl to data out when the ctl change merely enables the output flop update whose data was already established. ?25ns [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 19 of 38 slave fifo interface synchronous slave fifo timing figure 10. synchronous slave fifo read mode toelz ctl designated as oe to low-z. time when external devices should stop driving data. 0?ns toehz ctl designated as oe to high-z 8 8 ns tclz ctl (non oe) to low-z. time when external devices should stop driving data. 0?ns tchz ctl (non oe) to high-z 30 30 ns tctlalpha ctl to alpha change at output ? 25 ns tctlbeta ctl to beta change at output ? 30 ns tdst addr/data setup when dle/ale not used 2 ? ns tdht addr/data hold when dle/ale not used 20 ? ns table 9. gpif ii timing in asynchronous mode [4] (continued) note the following parameters assume one state transition parameter description min max units notes synchronous read cycle timing pclk fifo addr t cyc t ch t cl t as slcs slrd t rds t rdh sloe flaga (dedicated thread flag for an) (1 = not empty 0= empty) t oelz data out high-z data driven:d n (an) t cdh t oez t oez 3 cycle latency from addr to data t co t oelz an am d n+1 (an) d n (am) d n+1 (am) d n+2 (am) slwr (high) t ah flagb (dedicated thread flag for am) (1 = not empty 0= empty) [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 20 of 38 synchronous slave fifo sequence description: 1. fifo address is stable and slcs is asserted 2. sloe is asserted. sloe is an output enable only, whose sole function is to drive the data bus. 3. slrd is asserted 4. the fifo pointer is updated on the rising edge of the pclk, while the slrd is asserted. this starts the propagation of data from the newly addressed location to the data bus. after a propagation delay of tco (measured from the rising edge of pclk) the new data value is present. n is the first data value read from the fifo. to have data on the fifo data bus, sloe must also be asserted. the same sequence of events is shown for a burst read. note for burst mode, the slrd# and sloe# are left asserted during the entire duration of the read. when sloe# is asserted, the data bus is driven (with dat a from the previously addressed fifo). for each subsequent rising edge of pclk, while the slrd# is asserted, the fifo poin ter is incremented and the next data value is placed on the data bus. [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 21 of 38 figure 11. synchronous slave fifo write mode synchronous write cycle timing pclk fifo addr t cyc t ch t cl t as slcs slwr data in high-z d n (an) t dh t ds t dh t ds t dh t wrs t wrh t peh pktend d n (am) d n+1 (am) d n+2 (am) sloe (high) an am t ah t pes flaga dedicated thread flag for an (1 = not full 0= full) t cflg flagb current thread flag for am (1 = not full 0= full) t cflg pclk fifo addr t cyc t ch t cl t as slcs slwr (high) data in high-z pktend sloe (high) an t ah flaga dedicated thread flag for an (1 = not full 0= full) flagb current thread flag for am (1 = not full 0= full) t peh t pes synchronous zlp write cycle timing t cflg [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 22 of 38 synchronous slave fifo write sequence description fifo address is stable and the signal slcs# is asserted external master/peripheral outputs the data onto the data bus slwr# is asserted while the slwr# is asserted, data is written to the fifo and on the rising edge of gthe pclk, the fifo pointer is incre- mented the fifo flog is updated after a delay of t wflg from the rising edge of the clock the same sequence of events is also shown for burst write note: forthe burst mode, slwr# and slcs# are left asserted for the entire duration of writing all the required data values. in this burst write mode, after th e slwr# is asserted, the data on the fifo data bus is written to the fifo on every rising edge of pclk. the fifo pointer is updated on each rising edge of pclk. short packet: a short packet can be committed to the usb host by using the pktend#. the external device/processor should be designed to assert the pktend# along with the last word of data and slwr# pulse corresponding to the last word. the fifoaddr lines have to be held constant during the pktend# assertion. zero length packet: the external device/processor can signal a zero length packet (zlp) to ez-u sb fx3, simply by asserting pktend#, without asserting slwr#. slcs# and address must be driven as shown in the above timing diagram. flag usage: the flag signals are monitored by the external processor for flow control. flag signals are outputs from ez-usb fx3 that may be configur ed to show empty/full/partial status for a dedicated thread or the current thread being addressed. . table 10. synchronous slave fifo parameters [5] parameter description min max units freq interface clock frequency ? 100 mhz tcyc clock period 10 ? ns tch clock high time 4 ? ns tcl clock low time 4 ? ns trds slrd# to clk setup time 2 ? ns trdh slrd# to clk hold time 0.5 ? ns twrs slwr# to clk setup time 2 ? ns twrh slwr# to clk hold time 0.5 ? ns tco clock to valid data ? 8 ns tds data input setup time 2 ? ns tdh clk to data input hold 0.5 ? ns tas address to clk setup time 2 ? ns tah clk to address hold time 0.5 ? ns toelz sloe# to data low-z 0 ? ns tcflg clk to flag output propagation delay ? 8 ns toez sloe# deassert to data hi z ? 8 ns tpes pktend# to clk setup 2 ? ns tpeh clk to pktend# hold 0.5 ? tcdh clk to data output hold 2 ? ns note three-cycle latency from addr to data/flags note 5. all parameters guaranteed by design and validated through characterization. [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 23 of 38 asynchronous slave fifo timing figure 12. asynchronous slave fifo read mode asynchronous slave fifo read sequence description fifo address is stable and the slcs# signal is asserted. sloe# is asserted. this results in the data bus being driven. slrd # is asserted. data from the fifo is driven on assertion of slrd#. this data is valid after a propagation delay of trdo from the falling edge of slrd#. fifo pointer is incremen ted on de-assertion of slrd# in the above diagram , data n is the first valid data read from the fifo. for data to appear on the data bus during the read cycle sloe# must be in an asserted state. slrd# and sloe# can also be tied together. the same sequence of events is also shown for a burst read. note: in burst read mode, during sloe# assertion, the data bus is in a driven state (data driven is from previously addressed fifo). on assertion of slrd# dat a from the fifo is driven on the data bus (sloe# must also be asserted) and the fifo pointer is incremented on de-assertion of slrd#. fifo addr t as slcs slrd t rdl sloe flaga dedicated thread flag for an (1=not empty 0 = empty) t oe data out high-z t ah d n (an) t rdo t oe t rdo t oh t oh t rdh t rdo t lz d n (an) d n (am) d n+1 (am) d n+2 (am) slwr (high) an am flagb dedicated thread flag for am (1=not empty 0 = empty) t rflg t flg [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 24 of 38 figure 13. asynchronous slave fifo write mode fifo addr t as slcs slwr t wrl data in high-z t ah d n (an) t wr s t wr s t wrh t wrh t wrh pktend d n (am) d n+1 (am) d n+2 (am) sloe (high) an am flaga dedicated thread flag for an (1=not full 0 = full) t wflg t wflg flagb dedicated thread flag for am (1=not full 0 = full) t flg t wrpe change twrpe definition to slwr# de-assert to pktend de-assert = 0ns min (this means that pktend should not be be deasserted be fore slwr#) note: pktend must be asserted at the same time as slwr#. asynchronous zlp write cycle timing fifo addr t as slcs slwr (high) data in high-z t ah sloe (high) an flaga dedicated thread flag for an (1=not full 0 = full) flagb dedicated thread flag for am (1=not full 0 = full) pktend t pel t peh t wflg t peh [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 25 of 38 asynchronous slave fifo write sequence description fifo address is driven and slcs# is asserted slwr# is asserted. slcs# must be asserted with slwr# or before slwr# is asserted data must be present on the bus twrs before the deasserting edge of slwr# de-assertion of slwr# causes th e data to be written from the data bus to the fifo and then fifo pointer is incremented the fifo flag is updated after the twflg from the de-asserting edge of slwr. the same sequence of events is shown for a burst write. note that in the burst write mode, on slwr# de-assertion, the data is written to the fifo an d then the fifo pointer is incre- mented. short packet: a short packet can be committed to the usb host by using the pktend#. the external device/processor should be designed to assert the pktend# along with the last word of data and slwr# pulse corresponding to the last word. the fifoaddr lines have to be held constant during the pktend# assertion. zero length packet: the external device/processor can signal a zero length packet (zlp) to ez-u sb fx3, simply by asserting pktend#, without asserting slwr#. slcs# and address must be driven as shown in the above timing diagram. flag usage: the flag signals are monitored by the external processor for flow control. flag signals are outputs from ez-usb fx3 that may be configur ed to show empty/full/partial status for a dedicated address or the current address. note 6. all parameters guaranteed by design and validated through characterization. table 11. asynchronous slave fifo parameters [6] parameter description min max units trdi slrd# low 20 ? ns trdh slrd# high 10 ? ns tas address to slrd#/slwr# setup time 7 ? ns tah slrd#/slwr#/pktend to address hold time 2 ? ns trflg slrd# to flags output propagation delay ? 35 ns tflg addr to flags output propagation delay 22.5 trdo slrd# to data valid ? 25 ns toe oe# low to data valid ? 25 ns tlz oe# low to data low-z 0 ? ns toh sloe# deassert data output hhold ? 22.5 ns twri slwr# low 20 ? ns twrh slwr# high 10 ? ns twrs data to slwr# setup time 7 ? ns twrh slwr# to data hold time 2 ? ns twflg slwr#/pktend to flags output propagation delay ? 35 ns tpei pktend low 7.5 ? ns tpeh pktend high 7.5 ? ns twrpe slwr# deassert to pktend deassert 0 ? [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 26 of 38 serial peripherals timing i 2 c timing figure 14. i 2 c timing definition [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 27 of 38 note 7. all parameters guaranteed by design and validated through characterization. table 12. i 2 c timing parameters [7] parameter description min max units notes i 2 c standard mode parameters fscl scl clock frequency 0 100 khz thd:sta hold time start condition 4 ? s tlow low period of the scl 4.7 ? s thigh high period of the scl 4 ? s tsu:sta setup time for a repeated start condition 4.7 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 250 ? ns tr rise time of both sda and scl signals ? 1000 ns tf fall time of both sda and scl signals ? 300 ns tsu:sto setup time for stop condition 4 ? s tbuf bus free time between a stop and start condition 4.7 ? s tvd:dat data valid time ? 3.45 s tvd:ack data valid ack ? 3.45 s tsp pulse width of spikes that must be suppressed by input filter n/a n/a i 2 c fast mode parameters fscl scl clock frequency 0 400 khz thd:sta hold time start condition 0.6 ? s tlow low period of the scl 1.3 ? s thigh high period of the scl 0.6 ? s tsu:sta setup time for a repeated start condition 0.6 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 100 ? ns tr rise time of both sda and scl signals ? 300 ns tf fall time of both sda and scl signals ? 300 ns tsu:sto setup time for stop condition 0.6 ? s tbuf bus free time between a stop and start condition 1.3 ? s tvd:dat data valid time ? 0.9 s tvd:ack data valid ack ? 0.9 s tsp pulse width of spikes that must be suppressed by input filter 0 50 ns i 2 c fast mode plus parameters (not supported at i2c_vddq=1.2v) fscl scl clock frequency 0 1000 khz thd:sta hold time start condition 0.26 ? s tlow low period of the scl 0.5 ? s thigh high period of the scl 0.26 ? s tsu:sta setup time for a repeated start condition 0.26 ? s thd:dat data hold time 0 ? s tsu:dat data setup time 50 ? ns tr rise time of both sda and scl signals ? 120 ns tf fall time of both sda and scl signals ? 120 ns tsu:sto setup time for stop condition 0.26 ? s tbuf bus free time between a stop and start condition 0.5 ? s tvd:dat data valid time ? 0.45 s tvd:ack data valid ack ? 0.45 s tsp pulse width of spikes that must be suppressed by input filter 0 50 ns [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 28 of 38 i 2 s timing diagram figure 15. i 2 s transmit cycle note 8. all parameters guaranteed by design and validated through characterization. table 13. i 2 s timing parameters [8] parameter description min max units tt i 2 s transmitter clock cycle ttr ? ns ttl i 2 s transmitter cycle low period 0.35 ttr ? ns tth i 2 s transmitter cycle high period 0.35 ttr ? ns ttr i 2 s transmitter rise time ? 0.15 ttr ns ttf i 2 s transmitter fall time ? 0.15 ttr ns tthd i 2 s transmitter data hold time 0 ? ns ttd i 2 s transmitter delay time ? 0.3tt ns note tt is selectable through clock gears. max ttr is designed for 96 khz codec at 32 bits to be 326 ns (3.072 mhz). [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 29 of 38 spi timing specification figure 16. spi timing lsb lsb msb msb lsb lsb msb msb t lead t sck t sdd t hoi t wsck t wsck t lag t d v t rf t ssnh t dis t sdi t lead t sck t wsck t wsck t lag t rf t ssnh t sdi t dis t dv t hoi ssn (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) ssn (output) sck (cpol=0, output) sck (cpol=1, output) miso (input) mosi (output) spi master timing for cpha = 0 spi master timing for cpha = 1 t di t di [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 30 of 38 reset sequence the hard reset sequence requirements for ez-usb fx3 are specified here. notes 9. all parameters guaranteed by design and validated through characterization. 10. depends on lag and lead setting in spi_config register. table 14. spi timing parameters [9] parameter description min max units fop operating frequency 0 33 mhz tsck cycle time 30 ? ns twsck clock high/low time 13.5 ? ns tlead ssn-sck lead time 1/2 tsck [10] -5 1.5tsck [10] + 5 ns tlag enable lag time 0.5 1.5 tsck [10] +5 ns trf rise/fall time ? 8 ns tsdd output ssn to valid data delay time ? 5 ns tdv output data valid time ? 5 ns tdi output data invalid 0 ? ns tssnh minimum ssn high time 10 ? ns tsdi data setup time input 8 ? ns thoi data hold time input 0 ? ns tdis disable data output on ssn high 0 ? ns table 15. reset and standby timing parameters parameter definition conditions min (ms) max (ms) trpw minimum reset# pulse width clock input 1 ? crystal input 5 ? trh minimum high on reset# ? 5 ? trr reset recovery time (after which boot loader begins firmware download) ?1? tsby time to enter standby/suspend (from the time main_clock_en/ main_power_en bit is set) ??1 twu time to wakeup from standby clock input 1 ? crystal input 5 ? twh minimum time before standby/suspend source may be reasserted ?5? [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 31 of 38 figure 17. reset sequence ball map figure 18. ball map for ez-usb fx3 (top view) vdd (core) xvddq xtalin/ clkin reset # mandatory reset pulse hard reset trpw trh standby/ suspend source standby/suspend source is asserted (main_power_en/ main_clk_en bit is set) standby/suspend source is deasserted tsby twu xtalin/ clkin must be stable before exiting standby/suspend trr twh 12 34567891011 a u3vssq u3rxvddq ssrxm ssrxp sstxp sstxm avdd vss dp dm nc b vio4 fslc[0] r_usb3 fslc[1] u3txvddq cvddq avss vss vss vdd trst# c gpio[54] gpio[55] vdd gpio[57] reset# xtalin xtalout r_usb2 otg_id tdo vio5 d gpio[ 50] gpio[ 51] gpio[ 52] gpio[ 53] gpio[ 56] clkin_32 clkin vss i2c_gpio[ 58] i2c_gpio[ 59] o[ 6 0] e gpio[ 4 7] vss vio3 gpio[49] gpio[48] fslc[2] tdi tms vdd vbatt vbus f v io2 gpio[ 45] gpio[ 4 4 ] gpio[ 4 1] gpio[ 4 6] tck gpio[ 2 ] gpio[ 5] gpio[ 1] gpio[ 0 ] v dd g vss gpio[ 4 2] gpio[ 4 3 ] gpio[ 3 0 ] gpio[ 2 5] gpio[ 2 2] gpio[ 2 1] gpio[ 15] gpio[ 4] gpio[ 3 ] vss h v dd gpio[ 3 9] gpio[ 4 0 ] gpio[ 3 1] gpio[ 2 9] gpio[ 2 6] gpio[ 2 0 ] gpio[ 2 4] gpio[ 7] gpio[ 6 ] v io1 j gpio[ 3 8 ] gpio[ 3 6] gpio[ 3 7] gpio[ 3 4 ] gpio[ 2 8] gpio[ 16] gpio[ 19 ] gpio[ 14] gpio[ 9] gpio[ 8 ] v dd k gpio[ 35] gpio[ 33] vss vss gpio[27] gpio[23] gpio[18] gpio[17] gpio[13] gpio[12] gpio[10] l vss vss vss gpio[32] vdd vss vdd int# vio1 gpio[11] vss [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 32 of 38 pin description table 16. pin list pin i/o name description gpifii (vio1 power domain) gpif?ii interface slave fifo interface f10 vio1 i/o gpio[0] dq[0] dq[0] f9 vio1 i/o gpio[1] dq[1] dq[1] f7 vio1 i/o gpio[2] dq[2] dq[2] g10 vio1 i/o gpio[3] dq[3] dq[3] g9 vio1 i/o gpio[4] dq[4] dq[4] f8 vio1 i/o gpio[5] dq[5] dq[5] h10 vio1 i/o gpio[6] dq[6] dq[6] h9 vio1 i/o gpio[7] dq[7] dq[7] j10 vio1 i/o gpio[8] dq[8] dq[8] j9 vio1 i/o gpio[9] dq[9] dq[9] k11 vio1 i/o gpio[10] dq[10] dq[10] l10 vio1 i/o gpio[11] dq[11] dq[11] k10 vio1 i/o gpio[12] dq[12] dq[12] k9 vio1 i/o gpio[13] dq[13] dq[13] j8 vio1 i/o gpio[14] dq[14] dq[14] g8 vio1 i/o gpio[15] dq[15] dq[15] j6 vio1 i/o gpio[16] pclk clk k8 vio1 i/o gpio[17] ctl[0] slcs# k7 vio1 i/o gpio[18] ctl[1] slwr# j7 vio1 i/o gpio[19] ctl[2] sloe# h7 vio1 i/o gpio[20] ctl[3] slrd# g7 vio1 i/o gpio[21] ctl[4] flaga g6 vio1 i/o gpio[22] ctl[5] flagb k6 vio1 i/o gpio[23] ctl[6] gpio h8 vio1 i/o gpio[24] ctl[7] pktend# g5 vio1 i/o gpio[25] ctl[8] gpio h6 vio1 i/o gpio[26] ctl[9] gpio k5 vio1 i/o gpio[27] ctl[10] gpio j5 vio1 i/o gpio[28] ctl[11] a1 h5 vio1 i/o gpio[29] ctl[12] a0 g4 vio1 i/o gpio[30] pmode[0] pmode[0] h4 vio1 i/o gpio[31] pmode[1] pmode[1] l4 vio1 i/o gpio[32] pmode[2] pmode[2] l8 vio1 i/o int# int#/ctl[15] ctl[15] c5 cvddq i reset# reset# reset# io2 (vio2 power domain) gpif ii (32-bit data mode) k2 vio2 i/o gpio[33] dq[16] gpio j4 vio2 i/o gpio[34] dq[17] gpio k1 vio2 i/o gpio[35] dq[18] gpio j2 vio2 i/o gpio[36] dq[19] gpio j3 vio2 i/o gpio[37] dq[20] gpio [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 33 of 38 j1 vio2 i/o gpio[38] dq[21] gpio h2 vio2 i/o gpio[39] dq[22] gpio h3 vio2 i/o gpio[40] dq[23] gpio f4 vio2 i/o gpio[41] dq[24] gpio g2 vio2 i/o gpio[42] dq[25] gpio g3 vio2 i/o gpio[43] dq[26] gpio f3 vio2 i/o gpio[44] dq[27] gpio f2 vio2 i/o gpio[45] gpio io3 (vio3 power domain) gpif ii - 32 (fx3)+uart+i2s gpio+i2s uart+spi+ i2s f5 vio3 i/o gpio[46] gpio gpio gpio dq[28] gpio uart_rts e1 vio3 i/o gpio[47] gpio gpio gpio dq[29] gpio uart_cts e5 vio3 i/o gpio[48] gpio gpio gpio dq[30] gpio uart_tx e4 vio3 i/o gpio[49] gpio gpio gpio dq[31] gpio uart_rx d1 vio3 i/o gpio[50] gpio gpio gpio i2s_clk gpio i2s_clk d2 vio3 i/o gpio[51] gpio gpio gpio i2s_sd gpio i2s_sd d3 vio3 i/o gpio[52] gpio gpio gpio i2s_ws gpio i2s_ws io4 (vio4) power domain d4 vio4 i/o gpio[53] spi_sck uart_rts gpio uart_rts gpio spi_sck c1 vio4 i/o gpio[54] spi_ssn uart_cts gpio uart_cts i2s_clk spi_ssn c2 vio4 i/o gpio[55] spi_miso uart_tx gpio uart_tx i2s_sd spi_miso d5 vio4 i/o gpio[56] spi_mosi uart_rx gpio uart_rx i2s_ws spi_mosi c4 vio4 i/o gpio[57] gpio gpio gpio i2s_mclk i2s_mclk i2s_mclk usb port (vbatt/vbus power domain) c9 vbus/ vbatt i otg_id otg_id usb port (u3txvddq/u3rxvddq power domain) a3 u3rxvddq i ssrxm ssrx- a4 u3rxvddq i ssrxp ssrx+ a6 u3txvddq o sstxm sstx- a5 u3txvddq o sstxp sstx+ usb port (vbatt/vbus power domain) a9 vbus/vbatt i/o dp d+ a10 vbus/vbatt i/o dm d- a11 nc no connect crystal/clocks (cvddq power domain) b2 cvddq i fslc[0] fslc[0] c6 avdd i/o xtalin xtalin c7 avdd i/o xtalout xtalout b4 cvddq i fslc[1] fslc[1] e6 cvddq i fslc[2] fslc[2] d7 cvddq i clkin clkin d6 cvddq i clkin_32 clkin_32 i2c and jtag (vio5 power domain) d9 vio5 i/o i2c_gpio[58] i 2 c_scl d10 vio5 i/o i2c_gpio[59] i 2 c_sda table 16. pin list (continued) pin i/o name description [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 34 of 38 e7 vio5 i tdi tdi c10 vio5 o tdo tdo b11 vio5 i trst# trst# e8 vio5 i tms tms f6 vio5 i tck tck d11 vio5 i/o o[60] charger detect output power e10 pwr vbatt b10 pwr vdd a1 pwr u3vssq e11 pwr vbus d8 pwr vss h11 pwr vio1 e2 pwr vss l9 pwr vio1 g1 pwr vss f1 pwr vio2 g11 pwr vss e3 pwr vio3 l1 pwr vss b1 pwr vio4 l6 pwr vss b6 pwr cvddq b5 pwr u3txvddq a2 pwr u3rxvddq c11 pwr vio5 l11 pwr vss a7 pwr avdd b7 pwr avss c3 pwr vdd b8 pwr vss e9 pwr vdd b9 pwr vss f11 pwr vdd h1 pwr vdd l7 pwr vdd j11 pwr vdd l5 pwr vdd k4 pwr vss l3 pwr vss k3 pwr vss l2 pwr vss a8 pwr vss precision resistors c8 vbus/vbatt i/o r_usb2 precision resi stor for usb2.0 (connect a 6.04 k +/-1% resistor between this pin and gnd) b3 u3txvddq i/o r_usb3 precision resistor for usb3.0 (connect a 200 +/-1% resistor between this pin and gnd) table 16. pin list (continued) pin i/o name description [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 35 of 38 package diagram figure 19. 121-ball fbga 10x10x1.2 diagram ordering information ordering code definition 001-54471 *b table 17. ordering information ordering code package type CYUSB3014-bzxi 121-ball bga cy marketing code: usb = usb controller usb company id: cy = cypress package type: bga 3 i temperature range : industrial base part number for usb 3.0 xxx bzx marketing part number [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 36 of 38 acronyms document conventions units of measure acronym description dma direct memory access hnp host negotiation protocol mmc multimedia card mtp media transfer protocol pll phase locked loop sd secure digital sd secure digital sdio secure digital input / output slc single-level cell spi serial peripheral interface srp session request protocol usb universal serial bus wlcsp wafer level chip scale package symbol unit of measure c degree celsius a microamperes s microseconds ma milliamperes mbps megabytes per second mhz mega hertz ms milliseconds ns nanoseconds ohms pf pico farad vvolts [+] feedback [+] feedback
preliminary CYUSB3014 document number 001-52136 rev. *h page 37 of 38 document history page document title: CYUSB3014 ez-usb ? fx3 superspeed usb controller document number: 001-52136 revision ecn orig. of change submission date description of change ** 2669761 vso/pyrs 03/06/09 new datasheet *a 2758370 vso 09/01/09 updated the part# fr om cyx01xxbb to cyusb3011-bzxi changed the title from ?advance? to ?advance information? in page 1, the second bullet (flexible host interface), add ?32-bit, 100 mhz? to first sub bullet. in page 1, changed the second bullet ?flexible host interface? to general programmable interface?. in page 1, the second bullet (flexible host interface), removed "dma slave support? and "mmc slave support with pass through boot" sub bullets. in page 1, third bullet, changed "50 a with core power" to "60 a with core power" in page 1, fifth bullet, added "at 1 mhz" in page 1, seventh bullet, added "up to 4mhz" to uart in page 1, applications section, move ?digital still cameras? to second line. in page 1, applications section, added ?machine vision? and industrial cameras? added ? to gpif and fx3. in page 1, updated logic block diagram. in page 2, section of ?functional overview?, updated the whole section. in page 2, removed the section of ?product interface? in page 2, removed the section of ?processor interface (p-port)? in page 2, removed the section of ?usb interface (u-port)? in page 2, removed the section of ?other interfaces? in page 2, added a section of "gpif ii" in page 2, added a section of "cpu" in page 2, added a section of "jtag interface" in page 2, added a section of "boot options" in page 2, added a section of "renumeration" in page 2, added a section of "power" in the section of ?package?, replaced ?west bridge usb 3.0 platform? by fx3. in the section of ?package?, added 0.8 mm pitch in front of bga. added pin list ( table 1 ) *b 2779196 vso/pyrs 09/29/09 features : added the thrid bullet ?fully accessible 32-bit arm9 core with 512kb of embedded sram? added the thrid line ?ez usb? software and dvk for easy code devel- opment? ta b l e 1 : pin 74, corrected to nc - no connect. changed title to ez-usb? fx3: superspeed usb controller *c 2823531 osg 12/08/09 added data sheet to the usb3.0 eros spec 001-51884. no technical updates. *d 3080927 osg 11/08/2010 changed status from advance to preliminary changed part number from cyusb3011 to CYUSB3014 added the following sections: power , configuration options , digital i/os , system level esd , absolute maximum ratings , ac timing parameters , reset sequence , package diagram added dc specifications table updated feature list updated pin list added support for selectable clock input frequencies. updated block diagram updated part number updated package diagram [+] feedback [+] feedback
document number 001-52136 rev. *h revised may 17, 2011 page 38 of 38 ez-usb? is a trademark and west bridge ? is a registered trademark of cypress semiconductor corp. all products and company names mentioned in this document may be the t rademarks of their respective holders. preliminary CYUSB3014 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 *e 3204393 osg 03/24/2011 updated slave fifo pr otocol and added zlp signaling protocol changed gpifii asynchronous tdo parameter changed async slave fifo toe parameter changed async slave fifo trdo parameter added tcoe parameter to gpifii sync mode timing parameters renamed gpifii sync mode tdo to tco and tdo_ss0 to tco_ss0 modified description of gpifii sy nc tco (previously tdo) parameter changed tah(address hold time) parameter in async slave fifo modes to be with respect to rising edge of slwr#/slrd# instead of falling edge. correspondingly, changed the tah number. removed 24 bit data bus support for gpifii. *f 3218493 osg 04/07/2011 minor ecn - release to web. no content changes. *g 3235250 gsz 04/20/2011 minor updates in features. *h 3217917 osg 04/06/2011 updated gpifii synchronous timing diagram. added spi boot option. corrected values of r_usb2 and r_usb3. corrected tck and trst# pull-up/pull-down configuration. minor updates to block diagrams. corrected synchronous slave fifo tdh parameter. document title: CYUSB3014 ez-usb ? fx3 superspeed usb controller document number: 001-52136 revision ecn orig. of change submission date description of change [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CYUSB3014

	To Download CYUSB3014 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .